FPGA Based Gaussian Pulse Shaping Filter Using Distributed Arithmetic Algorithm

Pulse shaping is utilized to increase transmission data rate without increasing the bandwidth or bit error rate. In this paper an efficient approach is presented to design and implement a high speed Gaussian pulse shaping filter for ISI removal. The proposed filter has been designed and simulated using Matlab, synthesized with Xilinx Synthesis Tool (XST), and implemented on Spartan 3E based 3s500efg320-5 FPGA device using DALUT algorithm. The developed Gaussian filter structure can operate at an estimated frequency of 116.306 MHz by utilizing 4% of Slices, 1% of Slice Flip Flops and 4 % LUTS of target FPGA device. Hence, high-speed multiplier less design of pulse shaping FIR filter is achieved. Keywords—DALUT, FPGA , GSM, GMSK, HDTV, MATLAB, XST